1. Field of the Invention
The present invention generally relates to design tools used in the design of complex electronic systems including a large number of switching devices, such as are found in modern high speed computer systems and components, and more particularly to a computer implemented method for high level analysis of simultaneous switching in order to compute noise in the earliest phases of design with minimal amounts of design data.
2. Description of the Prior Art
Simultaneous switching is one form of noise that can exist in switching circuits. It is caused by a significant number of drivers switching at the same time or within the same time window. The result is an increased current draw on the power supply. In some cases, this increased current draw can cause a dip or negative spike in the voltage supply to the chip. This dip in power supply voltage can propagate as noise through both active and quiet drivers. In a worst case scenario, an extreme power supply dip can prevent all circuits on a chip from functioning properly.
The higher the loop inductance of a package's power distribution, the more susceptible it is to simultaneous switching noise, and thus the more critical simultaneous switching analysis becomes. The noise margin or noise immunity is the measure of noise tolerance of a characteristic set of nets and drivers on a package. The larger the noise tolerance, the greater the amount of noise that can be withstood without adverse effects.
All of the concerns listed above apply equally to any semiconductor technology. The amount of noise generated is primarily determined by the device current switching rate. The higher di/dt causes larger noises and thus additional concerns about the compounded effects of this noise. With system speeds increasing from values on the order of 10 Mhz (megahertz) to the order of 100 Mhz, concerns about destructive simultaneous switching noise increase.
Noise, in general, can cause false switching. For the purpose of completeness, a brief explanation and example will be included here, demonstrating how simultaneous switching noise can cause false switching. Consider the simple case of an output gate array feeding an inverter as shown in FIG. 1A. The output voltage from the gate array of combinatorial logic gates at steady state is well defined for a known technology. If there were no noise, the input logic "1" to the inverter would be nearly the same as the output logic "1" from the gate array, as shown in FIG. 1B. Likewise, the logic "0" input to the inverter would be nearly the same level as the output logic "0" from the gate array. Note in FIG. 1B that the dotted shaded areas represent valid signal levels, both at the output of the array of gates, and at the input of the inverter. The cross hatched intermediate zone indicates that voltage levels are not sufficiently high or low to insure valid switching or maintain a desired state of the inverter receiver. Due to simultaneous switching noise, the actual level of the logic "1" reaching the inverter may be lower than the output from the gate array. Likewise, the logic "0" arriving at the inverter may be greater than the maximum logic "0" transmitted by the gate array. The difference between the lowest logic transmitted by the gate array and the minimum logic "1" acceptable to the inverter is the high input voltage noise margin. The difference between the highest logic "0" transmitted from the gate array and the highest logic acceptable by the inverter input is the low input voltage noise tolerance. When the logic "1" arriving at the inverter is less than the minimum allowable logic "1", that is defined by the logic high input range, the output state of the inverter can not be guaranteed, and the receiver may interpret its input as a logic " 0". Likewise, if the logic "0" arriving at the inverter were to be greater than the maximum allowable, as defined by the logical "0" low input range, then the receiver state will become indeterminate and may perceive its input as a logic "1". Whenever the steady state signal may enter the hatched intermediate zone, false switching may occur, and the current state is indeterminate.
As design performance is regularly pushed to new limits, more and more data needs to be transmitted faster and faster. With faster drivers, the potential for false switching due to induced simultaneous switching noise increases. Likewise, greater amounts of data need to be transmitted in the present aggressive design environment causing bus widths to continue to grow and further aggravating the simultaneous switching noise problem. The importance of simultaneous switching noise analysis continues to increase. In an effort to cut design times and bring products to market more swiftly, key analysis functions need to be made available earlier in the product design cycle. Simultaneous switching noise analysis has become increasingly important in product design. In an effort to maximize design efficiency, this analysis needs to be applied in the earliest stages or the product design cycle. The earlier this analysis is applied to a design, the sooner noise problems and be resolved, and perhaps prevented before they occur.
No existing software provides any means of computing simultaneous switching for early high level design. Existing simultaneous switching programs compute noise based on chips or components. This approach does not provide sufficient accuracy for today's higher speed clock requirements.